1. Field of the Invention
The present invention relates to an integrated circuit for implementing a desired electronic circuit through a CMOS process or the like, and particularly to an integrated circuit based on a macrocell scheme that forms an intended electronic circuit by combining a plurality of functional blocks with predetermined functions.
2. Description of Related Art
Conventionally, circuit designers have designed such a type of integrated circuits by considering transistor characteristics and the like to meet the intended functions of the electronic circuits. However, it takes unendurably long time for the designers to carry out the design of the recent high density integrated circuits by considering such details as the transistor characteristics. Thus, in common integrated circuits, basic functional blocks such as flip-flops, latches and the like are designed by functional block designers with considering the transistor characteristics so that the circuit designers can build the intended electronic circuits by only combining these functional blocks under certain conditions.
FIG. 7A shows a standard graphic symbol for a D flip-flop at a conventional functional block design level, and FIG. 7B shows its internal configuration. In these figures, the reference numeral 1 designates a data input terminal, 2 designates a clock input terminal, 3 designates a Q output terminal, and 4 designates a QC output terminal, where C denotes an inverted one.
In FIG. 7B, the reference numeral 13 designates a data inverter that inverts input data D applied to the data input terminal 1 and outputs it as inverted data DC; 14 designates a pre-stage latch circuit that latches the input data D and inverted data DC in response to the clock input to the clock input terminal 2, and outputs pre-stage latch data Q1 and inverted pre-stage latch data QC1; 15 designates a pre-stage latch circuit that latches the pre-stage latch data Q1 and inverted pre-stage latch data QC1 in response to the clock input to the clock input terminal 2, and outputs post-stage latch data Q2 and inverted post-stage latch data QC2; 9 designates a Q output buffer that inverts and amplifies the post-stage latch data Q2 to be output through the Q output terminal 3; and 10 designates a QC output buffer that inverts and amplifies the inverted post-stage latch data QC2 to be output through the QC output terminal 4.
Reference symbols TP1-TP13 and TPC1-TPC4 each designate a P-channel transistor formed on a CMOS semiconductor substrate, and symbols TN1-TN13 and TNC1-TNC4 each designate an N-channel transistor formed on the semiconductor substrate.
As is well-known, the D flip-flop latches the input data D at the rising edge of the clock C, and outputs it. The details of the operation will be omitted here because they will be described later.
With such an arrangement, the conventional integrated circuit must use a lot of transistors for each functional block, which hinders higher integration and lower power consumption.
More specifically, transistors disposed on the semiconductor substrate of the integrated circuit formed by the conventional macrocell scheme are formed in such a manner that each of them occupies a fixed area because it is not known which areas are assigned to which functional blocks. In addition, the transistors are each formed in a considerably large size to meet their maximum ratings. As a result, the functional blocks occupy unduly large areas on the substrate. It is not necessary for the functional blocks, however, to operate at such a large current, which holds true with the transistors of the flip-flops.
In addition, the functional blocks like the flip-flops that undergo synchronization by a clock signal constitute a very large part of the actually used functional blocks, and hence areas needed for clock wiring constitute one of the factors that hinder the high density integration.
Thus, the high density integration is hampered by the unduly large functional blocks or the redundant configuration of the clock system. As a result, it is not unlikely that the clock wiring cannot be formed between the functional blocks, which presents a problem of hindering a highly integrated electronic circuit.